(a) Fields of the Invention
The present invention relates to a transistor structure of a field effect transistor having a shallow trench isolation (STI), which can reduce stress applied from an STI portion to a channel region positioned below a gate electrode, and to its fabrication method.
(b) Description of Related Art
As the design rule of semiconductor devices shrinks, circuit integration therein increases dramatically to enable mounting of more than a hundred million field effect transistors on one chip. In order to fabricate such a chip, not only advancement of ultrafine processing technologies such as photolithography and etching requiring the processing accuracy of the order of several tens of nanometers, but also development of technologies for reducing variations in characteristics of individual transistors becomes an important challenge.
One of factors in variation in transistor characteristics includes stress applied from a shallow trench isolation (STI) portion to a channel region positioned below a gate electrode.
FIGS. 15A to 15F are sectional views showing a conventional STI formation flow. In the conventional formation method, as shown in FIG. 15A, first, a sacrificial oxide film 1502 and a mask nitride film 1503 are sequentially deposited on a silicon substrate 1501. Then, as shown in FIG. 15B, a photoresist 1504 is formed on the mask nitride film 1503, and the formed photoresist 1504 is patterned. Subsequently, as shown in FIG. 15C, using the photoresist 1504 as a mask, the mask nitride film 1503, the sacrificial oxide film 1502, and the silicon substrate 1501 are etched to form a trench 1505 with a predetermined depth. Next, as shown in FIG. 15D, after removal of the photoresist 1504, an inner wall of the trench 1505 is subjected to a thermal treatment at 1100° C. in an oxygen gas atmosphere. Thereby, the corner (upper edge) of the trench 1505 is rounded and simultaneously a side wall oxide film 1506 with a thickness of 10 nm is formed on the inner wall of the trench 1505. Next, an embedded oxide film 1507 filling the trench 1505 is deposited on the mask nitride film 1503. As shown in FIG. 15E, the embedded oxide film 1507 is polished by a chemical mechanical polishing (CMP) method, and then the upper portion of the embedded oxide film 1507 is removed by wet etching to adjust the amount of protrusion of the STI portion. As shown in FIG. 15F, finally, the mask nitride film 1503 and the sacrificial oxide film 1502 are removed to form an STI portion.
FIG. 16A is a schematic diagram showing cross-sectional structures of a MOS transistor and an STI portion. Table 1 shows the coefficients of linear expansion of semiconductor materials.
TABLE 1MaterialCoefficient of Linear Expansion [/° C.]SiO25.0E−07Si2.6E−06Ge5.8E−06
Referring to Table 1, the coefficient of linear expansion of silicon is about five times as great as that of silicon dioxide. Therefore, in the case where a silicon substrate 1601 is used as a substrate, for a period of time during which the temperature of a thermal treatment and the like in process changes from a thermal equilibrium state at a maximum temperature down to room temperature, compressive stress is being applied from an embedded oxide film 1606 of the STI portion to a channel region of the silicon substrate 1601 underlying a gate electrode 1602 (gate insulating film 1604).
FIG. 16B is a graph schematically showing the relation between the variation rate of driving current and the finger length 1605 obtained from the MOS transistor with a gate electrode length fixed. Note that in this specification, the term “finger length” indicates the distance in the direction of the gate length from the edge of the gate electrode to the edge of the STI portion. As can be seen from FIG. 16B, as the finger length 1605 decreases, the driving current of a p-channel transistor increases while the driving current of an n-channel transistor decreases. It is known that stress applied to a channel region changes carrier mobility in a transistor. To be more specific, workings of compressive stress on the channel region increase the mobility in the p-channel transistor and decrease the mobility in the n-channel transistor. On the other hand, workings of tensile stress thereon decrease the mobility in the p-channel MOS transistor and increase the mobility in the n-channel MOS transistor. According to data reported in the document (V. Chan et al., IEDM Tech. Dig. pp. 77-80 (2003).), decreasing the finger length from 1.2 μm to 0.2 μm increases the driving current of the p-channel MOS transistor by 23% and decreases the driving current of the n-channel MOS transistor by about 9%.
The change in driving current due to stress also depends on gate length. FIG. 16C is a graph schematically showing the relation between the variation rate of driving current and the gate length obtained from the MOS transistor with a finger length fixed. As shown in FIG. 16C, a transistor with a certain finger length has a gate size with a maximum variation rate of driving current. According to data reported in the document (V. Chan et al., IEDM Tech. Dig. pp. 77-80 (2003).), in the case of a finger length of 0.2 μm, a transistor with a gate length of 240 nm exhibits a maximum variation rate of driving current, and a decrease in gate length reduces variation in driving current.
As an approach to reducing stress applied from the STI portion to the channel region, Published Japanese translation of a PCT application No. 2004-530304 proposes formation of a buffer layer of a silicon oxynitride film at a boundary region between a silicon substrate and an embedded oxide film. U.S. Pat. No. 6,653,200 proposes use of thermal expansion coefficient of an embedded insulating film identical to that of a silicon substrate. This patent also proposes, as a trench-filling insulating film, a mixture of Al2O3 (25%)-SiO2 (75%) and a mixture of ZrO2 (30%)-SiO2 (70%).